CPU Registers

CPU Registers

1. What a Register Is

A register is a small, very fast storage location inside the CPU, built from flip-flops. It is the fastest memory in the hierarchy (access in one clock, < 1 ns, no bus trip) and holds the operands, addresses and intermediate results of the instruction being executed. Typical count: 8-32 general purpose registers in a CPU, each 16/32/64 bits wide.

2. Programmer-Visible vs Internal Registers

Group	Registers	Who uses them
User-visible (programmer-visible)	General purpose (AX/R0-R15), Accumulator, Index registers, Stack Pointer, Program Counter, Status/Flag register	The assembly programmer and the compiler
Internal (hidden)	MAR, MBR/MDR, Instruction Register, temporary operand registers, micro-program counters	Only the control unit — invisible to programs

3. Function of Each Register

Register	Typical width	Function
Program Counter (PC)	16 / 32 / 64 bits = address bus width	Address of the next instruction; incremented after every fetch; loaded with the branch target on JMP/CALL
Instruction Register (IR)	= word length (opcode + operand fields)	Holds the instruction being decoded right now
Memory Address Register (MAR)	= address bus width	Supplies the address to memory; its width fixes the addressable space $2^{n}$
Memory Buffer Register (MBR/MDR)	= data bus width	Buffer for data read from or written to memory
Accumulator (AC)	= word length	Default ALU operand and result register — the ALU always has one input from AC in simpler CPUs
General Purpose Registers (GPRs)	= word length	Fast operands/temporaries; used for register-to-register operations and variables
Index Register / Base Register	address width	Address arithmetic: effective address = base + index + displacement (arrays, structs, relocation)
Stack Pointer (SP)	address width	Points to the top of stack; PUSH decrements, POP increments (or vice versa depending on convention)
Status / Flags (PSW)	8-16 bits	Condition codes: C carry, Z zero, S sign, V overflow, P parity, plus interrupt-enable and mode bits
Segment registers (x86: CS, DS, SS, ES)	16 bits	Legacy base addresses for code, data and stack segments

4. How Registers Are Used in One Instruction

For the machine instruction ADD R1, R2 (meaning R1 = R1 + R2):

 1. PC     → MAR            address of the instruction
 2. memory → MBR → IR       instruction fetched
 3. PC     ← PC + 1         point to next instruction
 4. CU decodes IR           opcode = ADD, operands = R1, R2
 5. register file → ALU     operand 1 = R1, operand 2 = R2
 6. ALU adds                result + new flags (C, Z, S, V)
 7. ALU → R1                result written back to register file

Note that a register-to-register instruction touches no memory after the fetch, which is exactly why registers make code fast.

5. Register File, Windowing and Comparisons

Feature	Register	Cache	Main memory
Location	Inside CPU	On/near the core	On a memory module
Access time	< 1 ns (1 clock)	1-30 ns	50-100 ns
Size	100s of bytes	KB to tens of MB	GB
Addressed by	Name/encoding in the instruction (4-5 bits)	Address in cache tag	Full address on the bus
Speed of access	No bus cycle needed	Needs tag check	Full memory cycle

• The register file is a small multi-ported SRAM array that lets the ALU read two operands and write one result in the same cycle.
• Compilers try to keep loop counters and frequently used variables in registers ("enregistering"), spilling to the stack only when registers run out.
• RISC designs (ARM, MIPS) expose many registers and use register windows for fast function calls; CISC designs (x86) use fewer programmer-visible registers and rely more on memory operands.

6. Numericals to Remember

• A CPU with a 32-bit address bus must have a MAR of 32 bits, addressing $2^{32} = 4$ G locations; with a 64-bit data bus the MBR is 64 bits wide.
• If a register holds 16 bits and stores a signed number, its range is $-2^{15} = -32768$ to $+2^{15} - 1 = +32767$.
• To hold a fully expanded address of 1 MB memory, PC/MAR need at least 20 bits ($2^{20} = 1$ M).

7. Exam Points

• Draw/describe the CPU registers and give the function of each (PC, IR, MAR, MBR, AC, SP, flags) — 5-7 marks, very frequent.
• Differentiate PC and IR; MAR and MBR — 3 marks each.
• Explain the role of the accumulator and the effect of PC auto-increment — 3 marks.
• What are condition flags? Give any four with meaning — 3-5 marks.
• Compare registers, cache and main memory in speed and cost — 3-5 marks.
• Why does a register-to-register instruction execute faster than a memory-to-memory one? — 3 marks.