Memory: Architecture

Fundamentals of Computer Systems (8hrs) · Computer Fundamentals & Emerging Technologies

1. Basic Terms

Memory cell — the smallest storage unit that holds 1 bit (0 or 1). It is implemented by a flip-flop (SRAM) or a capacitor + transistor pair (DRAM).
Word — the group of bits the CPU reads/writes in one operation (e.g. 8, 16, 32, 64 bits). Word length decides the machine's "bit size".
Address — a unique number identifying a word/cell; the CPU refers to memory only by address.
Capacity = (number of words) × (bits per word), e.g. $4096 × 8 = 32$ Kbit.

2. Organisation of Main Memory

      CPU                                     MEMORY UNIT
  ┌─────────┐   ┌────────────┐          ┌────────────────────────┐
  │  ALU/CU │◄──┤    MAR     │──addr───►│ Decoder  ┌───────────┐ │
  │         │   ├────────────┤          │ (n → 2ⁿ) │ MEMORY    │ │
  │         │◄──┤    MBR     │◄─data───►│          │ ARRAY     │ │
  └─────────┘   └────────────┘          │          │ 2ⁿ × w    │ │
       ▲                                │          └───────────┘ │
       │ RD / WR / MFC ─── control bus ─┤  Read/Write logic      │
       └────────────────────────────────└────────────────────────┘

n address lines select one of $2^{n}$ locations; each location stores w bits.
Data bus width = $w$ (words transferred in parallel).
Control lines: RD, WR, Memory Function Complete (MFC).
Total addressable locations: $N = 2^{n}$ .

Design numerical: A memory chip has 12 address lines and an 8-bit word → $2^{12} = 4096 = 4$ K words × 8 bits = 32 Kbits = 4 KB.

3. Read and Write Operations

Read: CPU puts address in MAR → asserts RD → decoder selects the row → contents go to MBR → data bus → CPU (AC).
Write: CPU puts address in MAR, data in MBR → asserts WR → decoder enables the cell → data latched into the array.
Access time = time between the address being stable and the data being valid. Memory cycle time = access time + recovery time (write-back of a destructive read; DRAM needs it, SRAM does not).

4. RAM and ROM Families

Category	Sub-type	Built from	Volatility	Speed	Cost	Use
RAM	SRAM	6-transistor flip-flop	Volatile	Fastest, no refresh	High	Cache, registers
RAM	DRAM	1 transistor + capacitor	Volatile, needs refresh every few ms	Slower	Low, dense	Main memory
ROM	PROM	Fuse/anti-fuse, one-time programmable	Non-volatile	Slow	Low	Firmware (final build)
ROM	EPROM	Floating-gate, erased by UV light	Non-volatile	Slow	Moderate	Prototypes
ROM	EEPROM / Flash	Floating-gate, electrically erased	Non-volatile, byte/block erasable	Moderate	Moderate	BIOS, SSD, pen-drive, MCU

A modern PC uses DRAM for main memory and a small SRAM cache, with Flash for the BIOS — a hierarchy of mixed technologies rather than one type.

5. Memory Expansion and Addressing

To build a larger memory from small chips, two techniques are combined:

Word expansion (horizontal) — connect data lines of chips in parallel to extend word length: two 4K × 4 chips give 4K × 8.
Capacity expansion (vertical) — use the high-order address bits through a decoder to generate each chip's chip-select (CS).

Numerical: Build 64K × 8 using 16K × 8 chips → need $64/16 = 4$ chips and a 2-to-4 decoder on lines A15, A14.

6. Memory Map Idea

A memory map shows which addresses belong to which device. Example for an 8085-style system:

Address range	Size	Device
0000H-0FFFH	4 KB	Monitor ROM (BIOS)
1000H-1FFFH	4 KB	Video RAM
2000H-FFFFH	56 KB	User RAM

EEPROM/ROM is mapped at the reset vector so that the CPU finds its first instruction after power-on.

7. Exam Points

Draw and explain the organisation of main memory (MAR, MBR, decoder, array, buses) — 7 marks.
Differentiate SRAM and DRAM; RAM and ROM — 3-5 marks.
Non-volatile memories: PROM, EPROM, EEPROM with erasing method — 5 marks.
Numerical: address lines / word size / capacity, or number of chips needed for a given expansion — 3-5 marks.
Define access time and memory cycle time; why is DRAM slower than SRAM? — 3 marks.

Memory: Architecture