The Von-Neumann architecture

Fundamentals of Computer Systems (8hrs) · Computer Fundamentals & Emerging Technologies

1. Origin and the Stored Program Idea

Proposed by the mathematician John von Neumann in the 1945 "First Draft of a Report on the EDVAC". Its revolutionary idea was the stored program concept: a program is not wired into the machine (as in ENIAC) but is stored in memory as binary numbers, exactly like data. Because of this, the same hardware can run any program simply by loading different contents into memory — the basis of the general purpose computer. It is also called the Princeton architecture.

2. Key Features

Single memory for both instructions and data (unified / shared memory).
Binary representation of everything — data, instructions, addresses.
Sequential execution of instructions from the address in the Program Counter, unless a branch changes it.
Five functional units — input, memory, ALU, control unit, output; CU + ALU = CPU.
Single system bus (address + data + control) connecting CPU and memory; data movement is one word at a time.
Fetch-decode-execute cycle driven by a central clock.

3. Block Diagram

   ┌──────────────┐                          ┌───────────────────────────┐
   │ INPUT UNIT   │                          │           CPU             │
   │ keyboard,    │ ──── data/instructions ─►│  ┌────────┐  ┌──────────┐  │
   │ mouse, mic   │                          │  │  ALU   │  │   CU     │  │
   └──────────────┘                          │  └────────┘  └──────────┘  │
                                             │   PC  IR  MAR  MBR  AC    │
   ┌──────────────┐                          └─────────────┬─────────────┘
   │ OUTPUT UNIT  │ ◄──── results ──────────────────────────┘
   │ monitor,     │                                │  single bus
   │ printer      │                    ┌───────────┴────────────┐
   └──────────────┘                    │  MAIN MEMORY           │
                                       │  instructions + data   │
                                       └────────────────────────┘

4. Register-Transfer Description of One Instruction

The fetch phase (identical for every instruction):

  MAR ← PC            ; address of next instruction
  MBR ← M[MAR]        ; memory read
  IR  ← MBR           ; instruction goes to the decoder
  PC  ← PC + 1        ; point to the following instruction

Decode — CU separates the opcode and the operand addresses and decides the operation.
Execute — e.g. for ADD 500:

  MAR ← 500 ; MBR ← M[MAR] ; AC ← AC + MBR ; flags updated

Store — for STA 600: MAR ← 600 ; M[MAR] ← AC.

Total instruction time (four phases):

T_{cyc} = T_1 + T_2 + T_3 + T_4

5. The Von Neumann Bottleneck

Because instructions and data travel over the same bus and the same memory, the CPU must wait for one transfer at a time. The machine is throttled by memory bandwidth rather than by the ALU — this is the famous Von Neumann bottleneck. Formally, throughput is limited by the single shared path:

BW_{max} ≈ \text{word width} / \text{bus cycle time}

Consequences: a slow memory starves a fast CPU; adding ALUs does not help. Remedies: cache memory (keep the working set close), Harvard-style separate instruction/data caches, wider/multiple buses, memory interleaving, prefetching, pipelining and, at a higher level, parallelism.

6. Von Neumann vs Harvard Architecture

Aspect	Von Neumann	Harvard
Memory	Common for data + code	Physically separate data and instruction memory
Buses	One shared bus	Separate buses (can fetch instruction and read data at the same time)
Speed	Bottlenecked by the shared path	Faster, no structural hazard
Flexibility	Code can be modified/loaded freely (compiler-friendly)	Code memory usually fixed (firmware style)
Hardware cost	Cheaper, simpler	More pins and wiring
Examples	Most PCs (x86, AMD64 are von Neumann with Harvard-style caches)	8051, PIC, AVR, ARM Cortex-M (modified Harvard)

7. Advantages and Limitations

Advantages: simple and cheap design; single memory to manage; program and data treated uniformly so any program can be loaded; gives birth to general purpose computing and, later, to compilers and OSs.
Limitations: the bottleneck; instructions and data can collide (a buggy program could overwrite its own code — also the root of many security exploits); sequential execution wastes the parallelism available in the hardware.

8. Exam Points

State and explain the Von Neumann architecture with a block diagram — 7 marks, very frequent.
What is the stored program concept? Why is it important? — 3-5 marks.
Explain the Von Neumann bottleneck and how cache/pipelining/separate buses reduce it — 5 marks, very frequent.
Differentiate Von Neumann and Harvard architectures — 5 marks.
List the features and limitations of the Von Neumann model — 5 marks.
Draw the fetch-decode-execute cycle with register transfers or micro-operations — 5 marks.

The Von-Neumann architecture