Answer: (ii) Fetch

Instruction execution cycle: Fetch → Decode → Fetch Operands → Execute → Write Back/Store. First step is Fetch where PC is placed in MAR, instruction fetched from memory to MDR/IR and PC incremented.

Answer: (i) Hardwired Control Unit

Explanation:

• Hardwired CU uses combinational circuits (AND, OR, gates, decoders) to generate control signals. It is fast because signals propagate through hardware without memory access.
• Disadvantage: Difficult to modify or add new instructions - requires redesign of wiring.
• Microprogrammed CU uses control store (microprogram) - slower (microinstructions fetch) but flexible/easy to modify.
• Cache Control Unit and MMU are not types of CPU control unit.

Hence faster but inflexible = Hardwired CU.

Answer: (iii) Program-controlled I/O (Programmed I/O)

Explanation:

• Programmed / Program-controlled I/O: CPU continuously polls status register (busy/done bit) in a loop until device is ready, then transfers data. Wastes CPU cycles (busy-waiting).
• Interrupt-driven I/O: Device interrupts CPU only when ready - no polling.
• DMA: Direct transfer between memory & device by DMA controller without CPU polling/intervention.
• Asynchronous I/O: Overlapped/non-blocking operation, not polling.

Hence CPU polling = Programmed I/O.

Answer: c) SISO

Explanation:
Standard Flynn + modern parallel architectures:

• SIMD - Single Instruction Multiple Data - vector/GPU - valid parallel architecture.
• MIMD - Multiple Instruction Multiple Data - multicore/multiprocessor - valid.
• Multi-core - multiple cores on one chip - valid parallel processor.
• SISO - Single Instruction Single Operand is not a standard taxonomy term (Flynn uses SISD - Single Instruction Single Data); SISO is distracter/incorrect.

Hence NOT a parallel processor architecture = SISO.

Answer: (i) DMA controller (intended question = WITHOUT processor involvement)

Explanation:

• Large block I/O via Programmed I/O burdens CPU (polling/interrupt per word).
• DMA (Direct Memory Access) controller steals/borrows bus and transfers large chunks directly between I/O and memory without continuous CPU involvement, only initial setup and final interrupt by CPU.
• The question wording "with involvement of the processor" is likely a typo; strictly with involvement would be (iv) None of the above. For "WITHOUT CPU involvement", answer is (i) DMA controller.

DMA registers: Address, Count, Control/Status - handles burst/cycle-stealing modes and bus arbitration.

Answer: (ii) Facilitates easy implementation of new instructions

Explanation:

• Microprogrammed CU stores control signals as microinstructions in control memory (ROM). New instructions added by updating microcode - flexible, easy to modify.
• Not faster than hardwired: hardwired is faster (combinational logic); microprogrammed is slower due to control memory access (so (i) is false).
• (iii) and (iv) are incorrect descriptions.

Hence microprogrammed CU's advantage = easy extensibility/modifiability.

Answer: (ii) RISC

Explanation:

• RISC (Reduced Instruction Set Computer): Aimed at reducing CPI / execution time per instruction via simple, fixed-length instructions, load/store architecture, hardwired control, pipelining - executes each instruction in ~1 cycle.
• CISC (Complex Instruction Set Computer): Aimed at reducing number of instructions/code size via complex variable-length instructions, microprogrammed control - but each instruction takes multiple cycles.
• ISA = Instruction Set Architecture (interface), ANNA = not relevant.

Hence architecture focused on time of execution = RISC.

Answer: (i) The I/O devices and the memory share the same address space.

Explanation:

• Memory-mapped I/O: No separate I/O addresses; I/O registers are mapped into memory address space. CPU uses same LOAD/STORE instructions for both memory and I/O, decoded by address.
• Isolated/ I/O-mapped I/O: Separate address spaces, requires special IN/OUT instructions (option ii describes isolated I/O).
• Options (iii) and (iv) are incorrect descriptions.

Advantage: no extra instructions; disadvantage: reduces memory address space available.

Answer: (i) Interrupt-vector table

Explanation:

• Interrupt Vector Table (IVT) is an array in low memory (e.g., 0x00000 in x86) storing addresses (vectors) of ISRs (Interrupt Service Routines) indexed by interrupt number/type.
• On interrupt, CPU uses interrupt number × entry size to fetch vector and jump to handler.
• Vector table (ii) is generic; Symbol link table is unrelated (linking).

Hence correct is Interrupt-vector table.

Answer: iii. Immediate addressing

Explanation:

• Immediate addressing: Operand value itself is encoded within instruction (e.g., MOV AX, 5, ADD #5,R1). No memory access needed.
• Direct addressing: Instruction holds address of operand in memory.
• Indirect addressing: Instruction holds address of address.
• Indexed addressing: Address = base + index register.

Hence directly specifies operand = Immediate.

Answer: (i) Immediate

Explanation:

• Immediate addressing mode - operand value is directly specified in instruction field itself (e.g., MVI A, 05H, ADD #5). No memory reference.
• Direct: specifies address of operand.
• Definite not standard; Relative: PC + offset.

Hence direct value = Immediate.

Answer: Effective Address calculation:

Given R1=1200, R2=4600
(i) Load 20(R1), R5 → Indexed/Displacement mode: EA = R1 + 20 = 1200+20 = 1220. Content at memory 1220 loaded into R5.
(ii) Add -(R2), R5 → Autodecrement mode: First R2 = R2 - word size (assume 4 for 32-bit or 1 for simplicity; textbook uses R2 = 4600-1 = 4599 if byte, or 4596 if word). If byte-addressable decrement by 2? Typically -(R) means R ← R - size, then EA = R (new). So EA = 4599 (byte) or 4596 (word), value at that address added to R5. If size unspecified, EA = R2 -1 = 4599.

Difference: Programmed I/O vs Interrupt-driven I/O (2 marks, ~120 words)

Feature	Programmed I/O	Interrupt-driven I/O
CPU involvement	CPU polls status register continuously (busy-wait)	CPU continues other work; device interrupts when ready
Efficiency	Wasteful - CPU idle in loop	Efficient - no polling
Hardware	No interrupt logic needed	Needs interrupt controller, vector, enable/disable
Response time	Slower for infrequent devices	Faster, immediate via ISR
Use case	Simple, low-speed transfers	Better for multiple / faster devices

Summary: Programmed I/O = synchronous polling; Interrupt-driven I/O = asynchronous, CPU is freed until interrupt signals data ready, then CPU vectors to ISR to handle transfer.

Answer: (iii) 1024

Calculation:
Required: $32K \times 32$ bit. Chip: $128 \times 8$ bit.

• Depth factor: $32K/128 = 32768/128 = 256$
• Width factor: $32/8 = 4$
• Total = $256 \times 4 = 1024$ chips.

Same as Q181.

Justification: Stack computer is zero-address machine; operands implicitly on top of stack (TOS). Instruction needs only opcode because addresses of operands are implied: e.g., ADD pops two top elements, adds, pushes result. No fields to specify registers/memory. Useful for expression evaluation (postfix). Trade-off: needs stack manipulation instructions.

MIPS and MFLOPS - Performance Measures

1. MIPS - Million Instructions Per Second:
$$MIPS = \frac{\text{Instruction Count}}{Execution\ Time \times 10^6} = \frac{f_{clock}}{CPI \times 10^6}$$
where $f_{clock}$= clock frequency, $CPI$= cycles per instruction.

Measures integer/overall CPU throughput. e.g., CPU @ 2 GHz with CPI=2: $MIPS = 2000/(2)=1000$ MIPS.

Limitations of MIPS:

• Depends on instruction set - one ISA's instruction does more work than another.
• Ignores instruction complexity and mix.
• Not reliable for comparing different architectures or compilers.

2. MFLOPS - Million Floating Point Operations Per Second:
$$MFLOPS = \frac{\text{No. of Floating Point Operations}}{Execution\ Time \times 10^6}$$
Measures capability for scientific/numerical workload (add, mul, div on floats). Higher MFLOPS = better for supercomputing.

Limitations: Only counts FP ops, ignores integer, branch, I/O; depends on program (Linpack, etc) and compiler optimization.

Comparison: MIPS $\approx$ general-purpose speed, MFLOPS $\approx$ scientific speed. MFLOPS rating typically lower than MIPS on same machine because FP ops take more cycles. Both are crude; today SPEC, CPI, execution time preferred.

Types of Interrupts:

1. Hardware vs Software Interrupt:

   • Hardware Interrupt: Generated externally by hardware devices (e.g., I/O device, timer) signalling CPU via INTR/NMI pins. Asynchronous to program.
   • Software Interrupt: Generated internally by executing INT n instruction. Synchronous, used for system calls and exception handling.

2. Maskable vs Non-Maskable Interrupt:

   • Maskable (INTR): Can be enabled/disabled by Interrupt Flag (IF). CPU can ignore if IF=0. Used for normal peripherals.
   • Non-Maskable (NMI): Cannot be disabled, always serviced (IF has no effect). For critical events like power failure, memory parity error.

3. Vectored vs Non-Vectored Interrupt:

   • Vectored: Interrupting device supplies vector address (branch address) directly. No polling needed. e.g., Intel RST, TRAP.
   • Non-Vectored: Vector address not supplied; CPU must poll/interrogate devices or jump to fixed address to identify source and then branch.

Answer: (iv) Register addressing (closest; more precisely Register Indirect)

Explanation: Register addressing uses register contents as address: EA = (R). Options given are confusing; (ii) Indirect addressing uses memory contents pointed by register. (iii) Direct uses address field directly. Register addressing means operand is in register. If question expects "Register indirect", choose Indirect or Register addressing. Here Register addressing (iv) is marked correct.

Zero-address instruction format: Instruction contains only opcode, zero address fields. Operand sources are implicit stack top. Architecture is stack-organized. Example: ADD, SUB, PUSH X, POP. Execution: PUSH A (A→TOS), PUSH B, ADD → pop TOS-1+TOS → push result. Advantage: short instruction, good for expression compilation; disadvantage: many stack operations, not flexible for random access.

Correct option: (iii) Both serial and parallel I/O

Note: Question prints intradata due to typo; read as intra-data / data transfer.

The I/O subsystem can transfer data either:

• Serial I/O - one bit at a time over single line, or
• Parallel I/O - multiple bits simultaneously over parallel lines.

Modern interfaces support both. Hence option (iii) is correct.

Condition Code Register (CCR) / Flag Register Uses:

CCR holds flags N, Z, V, C set by ALU after arithmetic/logic operation:

• N (Negative): N=1 if result MSB=1 (negative in 2's complement). Used for signed branch (BMI/BPL).
• Z (Zero): Z=1 if result = 0. Used to test equality (BEQ/BNE) and loop termination.
• V (Overflow): V=1 if signed 2's complement overflow (result exceeds range). Used for signed arithmetic error detection.
• C (Carry): C=1 if carry out from MSB (unsigned overflow) or borrow. Used for multi-precision addition/subtraction (ADC/SBC), unsigned comparison (BCS/BCC).

Uses: Conditional branching, decision making (CMP + flags), interrupt control, and detecting arithmetic errors without extra comparator.

Answer: (i) PC → MAR → Memory → MDR → IR

Typical Instruction Fetch Cycle (Fetch sequence) is:

1. PC → MAR: Program Counter holds address of next instruction. Its content is transferred to Memory Address Register (MAR).
2. MAR → Memory: MAR puts address on address bus, control unit issues READ.
3. Memory → MDR: Instruction word read from memory is loaded into Memory Data Register (MDR) / MBR.
4. MDR → IR: Instruction is then transferred to Instruction Register (IR) for decoding. Meanwhile PC is incremented (PC+1) to point to next instruction.

This is the standard von Neumann fetch path. Options (ii)-(iv) skip MAR or MDR and are incomplete.

Correct option: (i) PC → MAR → Memory → MDR → IR

Program Counter (PC):

The Program Counter is a CPU register that holds the memory address of the next instruction to be fetched for execution.

• At fetch, CPU reads instruction from address in PC, then PC is incremented (by instruction length, typically +1 or +4) to point to next sequential instruction.
• On branch/jump/call/return and interrupt, PC is loaded with target address, changing sequential flow.
• Essential for control flow and instruction sequencing; often called Instruction Pointer (IP).

Also used to calculate return address and for relative addressing.

Instruction Cycle Phases:

1. Fetch (F): Address in PC is put on bus, instruction fetched from memory to IR, PC incremented to next instruction.

2. Decode (D): Control unit decodes opcode in IR, identifies instruction type, operand addressing modes, and generates control signals; operands fetched from registers.

3. Execute (E): ALU/Control performs operation - arithmetic/logic, effective address calculation, branch target evaluation.

4. Memory/Interrupt Check: If instruction needs memory access (LOAD/STORE) data transfer occurs; finally CPU checks for pending interrupts - if any, save context and branch to ISR.

Cycle repeats as: $Fetch \rightarrow Decode \rightarrow Execute \rightarrow Interrupt\ Check$.

Interrupt-Initiated I/O:

In programmed I/O the CPU continuously polls the device status, wasting CPU cycles. In interrupt-initiated I/O the CPU does not poll.

• I/O device informs CPU of its readiness / completion by asserting an interrupt signal (INTR).
• CPU continues executing its current program; when interrupt is acknowledged, it suspends current work, saves PC/PSW, branches to Interrupt Service Routine (ISR) to transfer data.
• After ISR completes, CPU resumes original program.

Advantage: CPU utilization is greatly improved — CPU is free during I/O wait, interrupted only when device actually needs service. Basis for modern interrupt-driven and DMA systems.

Arithmetic Shift Left:

Arithmetic shift left shifts bits left by one position, LSB filled with 0, MSB (sign bit) preserved to maintain sign in 2's complement. Effectively multiplies signed number by 2.

Example: 0101 (5) -> 1010 (10), 1101 (-3) -> 1010 (-6) [MSB kept as sign].

If sign changes after shift (overflow), result is invalid and overflow flag V=1. Same operation as logical shift left except sign handling.

Properties of an Ideal ISA (Instruction Set Architecture):

1. Completeness – All essential operations (data transfer, arithmetic/logic, control, I/O) are provided so any computable function can be implemented.

2. Orthogonality – No special cases; any addressing mode can be used with any operation and any register. Instructions are independent and uniformly available.

3. Regularity / Symmetry – Uniform instruction format, consistent opcode field, operand interpretation. Simplifies decoding.

4. Efficiency – High code density, good performance, optimal use of registers/memory and support for high-level language constructs.

5. Expandability / Extensibility – Opcode space reserved for future instructions/extensions without redesign.

6. Compatibility & General Purpose – Balanced between hardware simplicity and software convenience; often includes support for interrupts, virtual memory and protection.

An ideal ISA thus simplifies compiler design, hardware decoding and pipelining while remaining complete and efficient.

Direct Memory Access (DMA):

Technique that allows an I/O device to transfer data directly to/from main memory without CPU intervention for each word.

• DMA controller (DMAC) takes over system buses (via Bus Request BR / Bus Grant BG, cycle stealing or burst mode).
• CPU initializes DMAC with start address, word count and direction; DMAC then handles the entire block transfer.
• CPU is free to do other work; interrupted only at start and completion.

Advantage: Much faster than programmed or interrupt-driven I/O for high-speed devices (disk, display) — especially for large block transfers.

Three-bus Structure – Add R4, R5, R6 (meaning $R4 \leftarrow R5 + R6$)

In three-bus organization, bus A and bus B supply operands and bus C carries result, so execution needs only one clock cycle (fetch/decode steps same as usual).

Sequence:

1. Fetch & Decode: PC_{out}, MAR_{in}, Read, WMFC; MDR_{out}, IR_{in}; PC_{inc}; Decode
2. Execute Add: R5_{outA}, R6_{outB}, ALU_{add}, R4_{inC}, End

Explanation: Contents of R5 placed on Bus A, R6 on Bus B, ALU adds them concurrently, result on Bus C is latched into R4.

Note: For single-bus it would need 3 steps: R5_{out}, Y_{in}; R6_{out}, Y+ R6 → Z; Z_{out}, R4_{in}. For two-bus: R5_{outA}, R6_{outB}, ALU → Z; Z_{out}, R4_{in}. Three-bus is fastest.

Hardware Polling:

A method to identify the interrupting device among multiple I/O devices using hardware logic instead of software.

A dedicated polling unit / hardware poller sequentially interrogates (polls) each device's interrupt flag via a common bus. It checks status bits one-by-one in priority order using combinational/sequential polling logic.

• Faster than software polling (which uses program loop to test each device).
• Flexibility intermediate between daisy-chain and vectored interrupt.
• On finding the requesting device, its address/vector is placed on bus and ISR is executed.

Contrast: Software polling – CPU executes a program to poll each device; Hardware polling – special hardware does it automatically.

Answer: (ii) CISC

x86 (Intel 8086 and its successors) belongs to CISC – Complex Instruction Set Computer.

• CISC characteristics shown by x86: variable-length instructions (1 to 15 bytes), large number of instructions & addressing modes, microprogrammed control, complex instructions that do multiple operations (e.g., REP MOVS), fewer registers with memory-to-memory operations.
• Contrasts with RISC (Reduced Instruction Set: fixed-length, load/store, many registers, hardwired control) like ARM, MIPS.
• Modern x86 externally is CISC but internally translates to RISC-like micro-ops (hybrid).

So option (ii) CISC is correct.

Hardwired vs Microprogrammed Control:

Hardwired Control	Microprogrammed Control
Uses combinational logic, gates, flip-flops, decoders - physically wired	Uses microcode stored in Control Memory (control store) - sequence of micro-instructions
Fast - propagation delay only	Slower - needs microinstruction fetch from control store
Difficult to modify - requires hardware redesign to add new instruction	Easy to modify - just change microcode
Complex design for complex ISA (large, inflexible)	Suitable for complex CISC, easy implementation of complex instructions
RISC typically uses hardwired	CISC (IBM 360, x86) often uses microprogrammed
No control memory needed	Requires control memory, MPC, microinstruction sequencer

In short: Hardwired = speed, inflexible; Microprogrammed = flexibility, slower, easy to extend.

Answer: (iv) DRAM (2 Marks)

Correct choice is (iv) DRAM — Dynamic RAM.

• DRAM stores bit as charge on a capacitor + transistor (1T1C). It is volatile, needs periodic refresh (every ~64ms) due to leakage, but is very dense and cheap → used as main memory.
• Contrast: SRAM uses 6T flip-flop, no refresh, faster but larger/costlier (cache); ROM/EEPROM are non-volatile.
• Hence for high-capacity main memory the technology referred to is DRAM — option (iv).

Answer: (ii) an address that points to a location in memory where the beginning address of the I/O service routine is stored

Vectored Interrupt: Device supplies the interrupt vector – a pointer/index. The vector is an address (or index into Interrupt Vector Table) that points to the starting address of the ISR (Interrupt Service Routine).

• Interrupt Vector Table (IVT) holds ISR addresses.
• On interrupt, CPU uses vector to fetch ISR address and jumps directly – no polling/search needed. Fastest identification.
• Contrasts with non-vectored where CPU must poll to find source.

So correct is (ii). Option (i) is vague/branch info – not correct; (iii) includes wrong (i), so false. Hence (ii) only.

Subroutine Uses (2 Marks)

A subroutine is a self-contained sequence of instructions called from different points in program to avoid code duplication.

Uses:

1. Modularity & Reuse: Common task (e.g. I/O, math) written once and called many times — saves memory, improves readability.
2. Return Address Management: On CALL addr, CPU saves return address (next PC) automatically — either in link register or on top of stack: SP ← SP-1, M[SP] ← PC, PC ← addr.
3. RET instruction: On RET, address popped back: PC ← M[SP], SP ← SP+1 and execution resumes after call.
4. Nesting & Recursion: Stack LIFO allows nested calls; parameters passed via registers/stack, and CALL/RET use stack pointer.

Thus subroutine supports structured programming with hardware stack mechanism.

Subroutine Call / Return Mechanism (2 Marks)

Uses stack to save return address and transfer control:

CALL (Call Subroutine):

1. Push return address: SP ← SP - 1; M[SP] ← PC (PC holds next sequential address after CALL)
2. Jump to subroutine: PC ← effective address of subroutine (branch target)

Assembly: CALL 2050H does above in one micro-sequence.

RET (Return):

1. Pop return address: PC ← M[SP]; SP ← SP + 1
2. Fetch resumes at saved location.

Stack LIFO supports nesting: each CALL pushes new address, each RET pops in reverse order, enabling recursion. Link register variant saves PC in LR instead of memory stack for low-overhead leaf calls.

Indirect Address Mode — EA = (Address Field) (2 Marks)

Effective Address in indirect mode is not the operand itself but the memory location where the operand address is stored.

• Definition: EA = M[A] or EA = (A) where A = address field of instruction. Instruction holds pointer to the operand address.
• Example: LOAD R1, @1000 where M[1000] = 5000 → EA = 5000 → R1 ← M[5000]
• Operation: Two memory accesses — 1st fetches address pointer M[A], 2nd fetches actual operand M[EA].
• ** advantage:** Allows large address space with short field, supports pointers/indirect arrays, but slower due to extra access — indicated by * or @ or ( ) notation.

Answer: (iii) Standard I/O interface — USB (2 Marks)

Correct choice is (iii) Standard I/O interface.

• USB (Universal Serial Bus) is the de-facto standard I/O interface for connecting peripherals (keyboard, mouse, storage, printer) to computer, hot-pluggable, serial, host-controlled.
• Features: 4-wire (Vcc/Gnd/D+/D-), differential signaling, tiered-star topology via hubs, up to 127 devices, versions 2.0/3.0/3.1 with 480 Mbps – 10 Gbps.
• Replaces legacy serial/parallel ports as universal I/O bus — hence option (iii).

Micro-operation Categories (2 Marks)

A micro-operation is an elementary operation performed on data in registers during one clock pulse. Four categories:

1. Register Transfer: Moves data between registers or between register and memory, without alteration. e.g. R1 ← R2, MAR ← PC, MDR ← M[MAR]. Triggered by control signals and bus.

2. Arithmetic Micro-operations: Performed by ALU. e.g. R3 ← R1 + R2, R1 ← R1 + 1 (increment), R2 ← R2 - 1 (decrement), Add with carry, Subtract.

3. Logic Micro-operations: Bitwise operations on registers. e.g. R1 ← R1 ∧ R2 (AND), R1 ← R1 ∨ R2 (OR), R1 ← not R1 (COMPLEMENT), XOR. Used for masking/clearing.

4. Shift Micro-operations: Shift/rotate register contents. e.g. R1 ← shl R1 (logical shift left), shr, ashl/ashr (arithmetic preserves sign), cir/cil (circular rotate). Used for serial transfer & multiply/divide by 2^n.

Subroutine vs Interrupt Service Routine (ISR):

Feature	Subroutine (Procedure)	Interrupt Service Routine (ISR / Interrupt Handler)
Invocation	Synchronous, explicitly called by program via CALL instruction	Asynchronous, invoked by hardware signal (INTR, NMI) or exception/trap. CPU diverts without program request
Control	Program has control - known location in code flow	Unpredictable timing, depends on external event / fault
Linkage	CALL saves return address (PC) on stack; RET returns	Interrupt logic saves PC and PSW/FLAGS automatically; return via IRET/RETI
Context Saving	Caller may save few registers (convention dependent)	Must save entire processor state (registers, flags) as interrupt can occur between any two instructions
Priority/Nesting	No priority concept, normal nesting via calls	Has priority; higher priority interrupts can preempt lower ISR; requires PIC (8259) arbitration
Synchronization	Blocking / sequential flow	Must be reentrant, short, ends with EOI to PIC; often disables interrupts at entry

Key Idea: Subroutine = software-initiated planned transfer; ISR = hardware-initiated event-driven transfer that transparently suspends current task. Example: CALL SORT vs keyboard ISR at vector 21h invoked on key press.

Answer: Bus Arbitration - Definition

Bus Arbitration is the process of resolving contention when multiple bus masters (CPU, DMA controller, processors in multiprocessor system, I/O controllers) simultaneously request control of the system bus. Since only one master can drive the bus at a time, an arbiter decides priority and grants bus access.

Need: Prevents collision and ensures orderly transfer.

Approaches:

1. Centralized Arbitration: Single hardware arbiter (e.g., priority encoder) grants bus via Bus Request ($BR$) / Bus Grant ($BG$) daisy-chain or independent requests.
2. Distributed Arbitration: Each master has its own arbitration logic and decides collectively (e.g., self-selection).

Common schemes: Daisy chaining, Polling, Independent Request (Parallel arbitration). Priority may be fixed, rotating, or dynamic.

In short, bus arbitration = mechanism to select one master among contenders to become next bus master.

Answer: (ii) facilitates easy implementation of new instructions

Correct option is (ii).

Explanation:
A microprogrammed control unit generates control signals from microinstructions stored in a Control Memory (control store). Each machine instruction is executed as a sequence of micro-operations defined by firmware.

• Why (ii) is correct: To add a new instruction, only the microprogram in control memory needs to be modified/extended. No hardware rewiring is required, so implementation of new instructions, complex CISC instruction sets, and design changes is flexible and easy. It also simplifies debugging via microcode changes.

• Why other options are wrong:

  • (i) is faster: False. Hardwired CU using combinational logic (gates, encoders) is faster because microprogrammed CU requires fetch of microinstruction from control memory. Microprogrammed is slower.
  • (iii) useful when every small program is to be run: Irrelevant. Control unit type has no relation to running small user programs.
  • (iv) usually refers to CU of microprocessor: False. Both types can be used in microprocessors; this is not a definition.

Hence microprogrammed CU trades speed for flexibility and ease of modification.

Addressing Modes - Detailed Explanation [14 Marks]

Addressing mode defines how the effective address (EA) of an operand is generated from the instruction. It determines where the operand is - in instruction itself, register, or memory. Efficient modes reduce instruction size and execution time.

---

1. Implied / Implicit Mode

Operand is implied by opcode itself. No address field.
Example: CLC (clear carry), HLT, STC. EA not needed.

2. Immediate Mode

Operand is literal value within instruction.
EA = - , Operand = instruction field

MOV AL, #20H    ; AL <- 20H
ADD R1, #10     ; R1 <- R1 + 10

Advantage: Fast (no memory fetch for operand). Use: constants.

3. Register Mode

Operand in CPU register. Field specifies register number.

MOV R1, R2      ; R1 <- R2
ADD AX, BX

Very fast - no memory access. Register Indirect variant: register holds memory address.

MOV AL, [BX]    ; AL <- M[BX]   (BX points to memory)
LDA (R1)        ; AC <- M[R1]

4. Direct / Absolute Mode

Instruction contains full memory address of operand.
EA = Address field , Operand = M[EA]

LDA 2500H       ; AC <- M[2500H]
STA 3000H

Simple but needs large address field → long instruction, limited addressability.

5. Indirect Mode

Address field contains address of address. Need two memory accesses.
EA = M[Address field]

LDA @2000H      ; If M[2000H]=3000H, then AC <- M[3000H]
MOV R1, @(R2)   ; variant: register indirect with indirection bit

Useful for pointers, but slower.

6. Indexed Mode

EA = Base (in address field) + Index Register

LDX 1000H(X2)   ; EA = 1000H + X2 , AC <- M[EA]

Variants: Auto-index (increment/decrement after access) for arrays/loops.
Use: Array access A[i] → base address of A + i.

7. Based / Base-Register Mode

EA = Base Register + Displacement

MOV AL, [BX+500H]  ; EA = BX + 500H (8086 based mode)

Similar to indexed but base is pointer (e.g., base of array/structure), displacement is offset.

8. Relative / PC-Relative Mode

EA = PC + Displacement (offset relative to current instruction)

BEQ  20H       ; branch to PC+20H if equal
JMP  LABEL     ; LABEL is displacement from PC

Advantage: Position-independent code, short displacement field.

9. Stack Mode

Operand on top of stack (SP points to TOS). Implicit.

PUSH AX       ; SP--, M[SP] <- AX
POP BX        ; BX <- M[SP], SP++

10. Autoincrement / Autodecrement (Register Indirect with update)

MOV (R1)+, R2   ; R1 points to operand, then R1++
MOV -(R1), R2   ; R1--, then access

Efficient for traversing arrays/strings.

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Comparison Table:

Mode	EA Generation	Memory Accesses	Example
Immediate	No EA	0	ADD #5
Direct	EA = A	1	LOAD 100
Indirect	EA = M[A]	2	LOAD @100
Register	EA = R	0	ADD R1,R2
Reg Indirect	EA = (R)	1	LOAD (R1)
Indexed	EA = A + (XR)	1	LOAD 100(X1)
Relative	EA = PC + Offset	1	BNE -10

Significance in Instruction Design: Choice affects instruction length, number of memory references, capability for relocatable code, handling of arrays/pointers, and pipeline efficiency. Modern RISC (e.g., ARM, MIPS) favors register, immediate, base+offset, and PC-relative; CISC (x86) supports rich set of modes.

8086 Example: MOV AX, [BX+SI+1000H] uses based-indexed with displacement: EA = (BX)+(SI)+1000H.

Effective addressing is hardware implemented via 2's complement adder in address generation unit before memory access.

Why Read ($\overline{MEMR}$/$\overline{IOR}$) and Write ($\overline{MEMW}$/$\overline{IOW}$) Lines in DMA Controller are Bidirectional [14 Marks]

1. Background - 8237 / Generic DMAC and Bus Master Concept

System bus has control lines $\overline{MEMR}$, $\overline{MEMW}$, $\overline{IOR}$, $\overline{IOW}$ (or unified $\overline{RD}$, $\overline{WR}$). Normally CPU is bus master and drives these lines as outputs to command memory/I/O.

During DMA, DMAC becomes bus master after Bus Request ($HRQ$/$BUSREQ$) → Bus Grant ($HLDA$/$BUSACK$) handshake. The direction of $\overline{RD}$/$\overline{WR}$ reverses depending on who is master.

Hence DMAC pins are bidirectional (open-drain with direction control): sometimes input, sometimes output.

2. When DMAC is Bus Slave - Lines are INPUTS

Condition: CPU is bus master, DMAC is not performing DMA (Idle or Programming mode). CPU addresses DMAC as an I/O device via its chip select ($\overline{CS}$) and register addresses (A0-A3).

Purpose as Inputs: CPU programs DMAC's internal registers:

• DMA Address Register (starting address)
• Terminal Count / Word Count Register
• Mode Register, Command Register, Mask Register, Request Register

Operations:

• CPU performs I/O Write to DMAC: $\overline{IOW}$ (= $\overline{WR}$) = 0 as input to DMAC + $\overline{CS}$=0 → data D0-D7 latched into DMAC register. Example: OUT 0BH, AL to write Mask Register.
• CPU performs I/O Read from DMAC: $\overline{IOR}$ (= $\overline{RD}$) = 0 as input → DMAC drives data bus with status / remaining count register contents for CPU to read. Example: IN AL, 08H to read Status Register.

Without input mode, CPU could not initialize DMA channel (source, destination, count, transfer type) before starting.

3. When DMAC is Bus Master - Lines are OUTPUTS

Condition: DMAC has acquired bus ( $HLDA=1$, $AEN=1$, CPU tristates its buses). Now DMAC drives address bus and control lines to perform data transfer between Memory and I/O without CPU.

Purpose as Outputs - Two Types of DMA Transfer:

• DMA Read (Memory → Peripheral): DMAC asserts $\overline{MEMR}$ (or $\overline{RD}$ as output, low) to read memory and $\overline{IOW}$ to write to I/O device in same bus cycle (or two cycles in flyby vs. two-cycle DMA). Data flows memory → DMAC → I/O.
• DMA Write (Peripheral → Memory): DMAC asserts $\overline{IOR}$ to read peripheral and $\overline{MEMW}$ to write to memory. Data flows I/O → memory.
• Memory-to-Memory (in 8237): $\overline{MEMR}$ and $\overline{MEMW}$ sequentially asserted.

Thus as outputs, they act exactly as CPU's control signals would, commanding the memory and I/O participants.

4. Summary Diagram (Conceptual)

         CPU (Master)  -------- IOR/IOW / MEMR/MEMW --------> DMAC (Slave) : INPUT mode (Program)
                                         |
         DMAC (Master) -------- MEMR/MEMW , IOR/IOW --------> Memory & I/O : OUTPUT mode (Transfer)
                              (controls bus)

Internal direction control via Bus Master Enable logic: when $HLDA=1$ & $AEN$ active → buffers set to output; otherwise inputs. Shared pins save package pins and reflect that bus control is mutually exclusive - only one master drives at a time.

Key Advantage: Single set of control lines serves dual role → reduces interconnect and allows seamless hand-shaking: CPU configures DMAC as peripheral, then DMAC uses same lines as master to orchestrate high-speed block transfers (≈ 1.6 MB/s in 8237), freeing CPU.

Exam Tip: Always mention both modes with concrete instruction example (OUT/IN) for input, and Flyby transfer example for output.

DMA Controller Initialization for DMA Data Transfer (14 Marks)

1. Introduction - What is DMA?

Direct Memory Access (DMA) allows I/O devices to transfer data directly to/from main memory without continuous CPU intervention. CPU only initializes the DMA controller, then DMA handles the transfer via cycle stealing / bus mastering, freeing CPU for other work.

Ideal for high-speed transfers: Disk, Network, Audio/Video, ADC.

Without DMA, CPU does programmed I/O - fetch each byte, poll status - very inefficient.

2. DMA System Block Diagram

                    SYSTEM BUS (Data, Address, Control)
     ┌─────────────────────────────────────────────────────────────────┐
     │                                                                 │
     │   ┌───────┐      ┌──────────────┐      ┌────────────┐  ┌──────┐ │
     └──►│  CPU  │◄────►│ DMA Controller│◄────►│   Memory   │  │ I/O  │ │
         └───┬───┘      │  (8237/82357) │      └────────────┘  │Device│ │
             │          │ ┌───────────┐ │                     └──────┘ │
             │  HOLD/HLDA│ │ Registers │ │                            │
             │◄─────────►│ │ - CAR     │ │                            │
             │          │ │ - CWCR    │ │  DREQ ──► Peripherals      │
             │          │ │ - Mode Reg│ │  DACK ◄── request/ack      │
             │          │ │ - Command │ │  HRQ/HLDA to CPU           │
             └──────────┴─┴───────────┴─┴──────────────────────────────┘

Detailed DMA Controller Inside:
┌─────────────────────────────────────────┐
│  DMA Controller (4 channels example)    │
│ ┌──────────────┐ ┌──────────────────┐   │
│ │ Channel Logic│ │ Address Register │   │
│ │ 0-3          │ │ (16/32 bit) CAR  │   │
│ ├──────────────┤ │ Count Register   │   │
│ │ Mode Register│ │ (CWCR)           │   │
│ │ Command Reg  │ │ Data Buffer      │   │
│ │ Status Reg   │ │ Timing & Control │   │
│ │ Request Reg  │ │ Priority Encoder │   │
│ └──────────────┘ └──────────────────┘   │
└─────────────────────────────────────────┘

Signals: HRQ (Hold Request) -> CPU HOLD, HLDA <- CPU, DREQ (DMA Request from I/O), DACK (DMA Acknowledge), MEMR/MEMW, IOR/IOW, AEN (Address Enable), ADSTB

Connections: DMA sits between CPU, Memory and I/O. When idle, bus controlled by CPU. When active, DMA becomes bus master.

3. DMA Registers to be Initialized

Before any transfer, CPU (as program) must program following internal registers of DMA via I/O mapped writes (using CS, A0-A3, IOW):

Register	Purpose	Example
Starting Address Register (CAR)	Base address in memory where transfer starts	0x2000
Count Register (CWCR / Terminal Count)	Number of bytes/words to transfer -1	N-1 (e.g., 1023 for 1KB)
Mode Register	Transfer type: Read/Write/Verify, Auto-init, Address inc/dec, Demand/Single/Block	0x58 = Block, Inc, Write
Command Register	Controller enable/disable, priority (fixed/rotating), DREQ sense, memory-to-memory	0x00
Mask Register	Mask/unmask channel, enable DREQ	Clear mask
Request Register	Software request (for M-M transfer)

For 8237A: 4 channels, each 16-bit address + 16-bit count + 6-bit mode.

4. Step-by-Step Initialization Sequence

Assumption: Want to transfer 1KB from Disk (I/O port) to Memory address 0x20000 using Channel-1 Burst/Block mode.

Phase A: CPU Preparation

1. CPU executes setup routine with interrupts disabled (or handling).
2. CPU checks DMA idle - reads Status Register - ensure no ongoing transfer, channel not masked busy.

Phase B: Programming DMA (CPU as master, DMA as slave)

CPU writes via I/O instructions (OUT) to DMA port addresses:

Step 1: Send starting address

OUT CommandReg, 0x0C (clear First/Last flip-flop for 8237)
OUT AddressReg Ch1, Low Byte (0x00)
OUT AddressReg Ch1, High Byte (0x00)  -> also Page Register for A16-A23 if 24-bit (0x02)

Step 2: Send word count (N-1)

OUT CountReg Ch1, Low Byte (0xFF)  // 1024-1 = 1023 = 0x03FF
OUT CountReg Ch1, High Byte (0x03)

Step 3: Program Mode Register for Channel 1

Mode byte: [D7-D6=01][D5=0][D4=0][D3-D2=01][D1-D0=01]
           Channel select+ Transfer type (Write: I/O->Mem) + Auto-init 0 + Addr inc + Demand/Block
OUT ModeReg, 0x58

Step 4: Program Command Register

Bits: Fixed priority, Late write, DREQ active high, DACK active low
OUT CommandReg, 0x00

Step 5: Unmask Channel

OUT MaskReg, 0x01 (bit0=1 unmasks Ch1) or 0x01 -> using single mask: 0x01
Actually 8237 single mask: bit2=0 -> unmask, bits1-0=01 -> Ch1 => 0x01

Phase C: Initiate Transfer

3. I/O device enabled: Disk controller programmed via its own registers (sector, drive) to be ready.
4. Device asserts DREQ1 (when data ready)
5. DMA asserts HRQ -> CPU responds HLDA -> CPU tristates buses (floats Address/Data/Control) -> DMA asserts AEN=1, takes bus mastership, signals HLDA to device?
6. DMA outputs memory address on bus from CAR, asserts DACK1 to device, MEMW + IOR (for I/O->Memory) or MEMR+IOW (Memory->I/O). Data moves directly without CPU register.
7. After each byte: CAR increment/decrement, Count decrement. Bus stays with DMA in Block mode until TC, else released per byte in Single mode.
8. When Count = 0xFFFF (roll-over) => Terminal Count (TC) reached, DMA pulses EOP*, raises interrupt TC, deasserts HRQ, releases bus, sets Status bit.

Phase D: Termination & CPU Resumes

• Status Register can be polled / interrupt: CPU ISR reads status, checks TC for channel, handling completion.
• If Auto-initialization set, registers reload original values for next block; else channel masked.
• CPU resumes: HLDA deasserted, clears AEN, regains bus.

5. Initialization Flow Chart

CPU Program Start
      │
      ▼
Disable DMA? Check Status Idle
      │
      ▼
Write Base Address → CAR + Page Reg
      │
      ▼
Write Block Length → CWCR
      │
      ▼
Write Mode Reg (DIR, TYPE, MODE)
      │
      ▼
Write Command Reg
      │
      ▼
Unmask Channel (Enable DREQ)
      │
      ▼
Program I/O Device registers
      │
      ▼
Device asserts DREQ → DMA HRQ → CPU HLDA
      │
      ▼
DMA Bus Master → Transfer (Cycle Steal/Block)
      │
      ▼
TC? → EOP/Interrupt → CPU ISR → Done

6. Transfer Modes Programmed During Init

• Single Mode: One byte per DREQ, release bus - fair to CPU
• Block/Burst Mode: Entire block in one HRQ - fastest
• Demand Mode: Until DREQ deasserted - e.g. disk not ready
• Cascade: Connect multiple controllers

7. Example 8086 + 8237 Connection

CPU 8237 pins: CLK, RESET, CS*, IOR*, IOW*, A0-A3, D0-D7 to bus via latch 8282/8286. HRQ to 8086 HOLD, HLDA from 8086, DREQ0-3 from peripherals, DACK0-3 back, AEN to bus controller 8288 to disable CPU addresses, ADSTB to latch high address.

8. Importance / Advantages

• CPU free for computation during transfer → ~10-100x faster for bulk data
• Near memory speed transfer (limited by memory cycle + bus)
• Essential for modern systems - integrated DMA in PCI/PCIe bus mastering, not just 8237.

Exam Tip: Always draw block diagram + label registers + stepwise OUT sequence. For 14 marks, include both diagram, table of registers, sequence code, and timing (HRQ/HLDA handshaking).

Instruction Execution Cycle & x86 Features (7M)

A) Instruction Execution Cycle (Instruction Cycle)

Each instruction goes through sequence called Instruction Cycle controlled by CU.

Start -> Fetch -> Decode -> (Operand Fetch) -> Execute -> Writeback -> Interrupt Check -> Next

1. Fetch Cycle (IF):

• PC holds address of next instruction. MAR <- PC, PC++ (PC = PC + instruction_length). Memory read MDR <- Memory[MAR]; IR <- MDR. Fetch brings opcode + operands. Also increment IC.

2. Decode Cycle (ID):

• CU decodes opcode in IR via decoder, identifies instruction type, addressing mode, operand locations. Generates control signals. For microprogrammed CU, fetches micro-routine.

3. Operand Fetch / Effective Address Calculation:

• If instruction uses memory operand: Compute EA = Base + Index*Scale + Displacement using ALU. For x86: EA = EBX + ESI*4 + 0x10. Fetch operand Operand <- Memory[EA] or Register.

4. Execute Cycle (EX):

• ALU performs operation. Examples: ADD AX,BX => AX <- AX+BX sets FLAGS; JMP => PC <- target; LOAD => etc. Takes 1 to many cycles depending on complexity (mul/div = multiple cycles).

5. Store / Write Back:

• Result written to destination (Register or Memory). Memory[EA] <- AC or Reg <- Result. Flags updated (ZF,SF,CF,OF).

6. Interrupt Check:

• After each instruction, CU checks INTR, NMI. If asserted and enabled, save PC/PSW to stack and branch to ISR vector.

States:

Non-interrupt : FETCH -> INDIRECT (if indirect addr) -> EXECUTE
Interrupt     : ... EXECUTE -> INTERRUPT (save PC, PC <- vector)

Machine Cycle vs State: Each phase may take multiple clock states (T1-T4). e.g., 8086 MOV AX, [BX] = 4 clocks fetch + 6 clocks EA + memory read.

Example - ADD AX, [3000H] on hypothetical CPU:
T1: MAR<-PC, T2: MDR<-Mem, IR<-MDR, PC++
T3: Decode ADD, MAR<-3000H
T4: MDR<-Mem[3000H], TMP<-MDR
T5: AC<-AX+TMP, FLAGS update, AX<-AC

B) Key Features of x86 Architecture

x86 (8086 family, IA-32, x86-64) is CISC:

1. Register Organization: 8086: 4 GPR AX,BX,CX,DX (each 16b, divisible into AH/AL), 4 index/pointer SP,BP,SI,DI, 4 segment registers CS,DS,SS,ES, IP, FLAGS. IA-32 adds 32-bit EAX-EDI, ESI, EIP; x86-64 adds RAX-R15 (64-bit) + 16 XMM/YMM.

2. Segmentation & Memory Addressing: Real Mode: Physical addr = Segment*16 + Offset (20-bit via overlapping segments, 1MB). Protected Mode (80286+): Segment selector + descriptor table (GDT/LDT) giving base, limit, protection. Paging (80386+): 2-level paging to 4KB pages.

3. CISC Instruction Set: Variable length 1-15 bytes, many addressing modes (register, immediate, direct, register indirect, based, indexed, based-indexed with displacement), ~ 1000 opcodes (string: MOVS, REP). Complex instructions: REP MOVSB, ENTER.

4. Arithmetic Capabilities: Support for 8/16/32/64-bit, BCD (DAA/DAS), floating point via separate x87 FPU stack (ST0-ST7, 80-bit extended), later SSE/AVX for SIMD.

5. Modes of Operation:

   • Real Mode (8086 compatible)
   • Protected Mode (multitasking, privilege levels Ring 0-3, virtual memory)
   • Virtual 8086 Mode
   • System Management Mode (SMM)
   • Long Mode (x86-64, 64-bit)

6. Little-Endian: Lower address stores LSB.

7. Stack Support: Hardware stack via SS:SP with PUSH/POP, CALL/RET.

8. Interrupt Architecture: 256 vectored interrupts (0-255), INTR (maskable), NMI, Exception handling, IDT.

9. Backward Compatibility: All x86 generations run 8086 code; extensions via CPUID.

10. Extensions: MMX, SSE/SSE2/SSE4, AVX/AVX512 (SIMD for multimedia), Virtualization (VT-x), 64-bit extension (AMD64).

Comparison: Vs RISC: higher code density, but complex decode -> micro-ops translation to RISC-like internally (since Pentium Pro) for pipelined execution.

Addressing Modes with Examples (7M)

Definition: Addressing mode specifies rule for calculating Effective Address (EA) or operand location. Field A in instruction does not always equal EA; mode bits tell CPU how to interpret it.

General equation: EA = Base + Index * Scale + Displacement + PC-relative, value loaded accordingly.

Why x86 has many modes? To support arrays, pointers, stack, constants efficiently.

1. Immediate Mode

Operand itself in instruction. EA not needed.
Op = A

Example: MOV AX, 1234H ; ADD R1, #10 -> Instruction contains 00001010.
Use: Constants. Fast, no memory extra fetch beyond instruction.

2. Register Mode (Register Direct)

Operand in register R. EA is register ID, not memory.

Example: MOV AX, BX ; ADD R1, R2 => R1 = R1 + R2
Fastest (internal), used heavily in load-store architecture.

3. Direct / Absolute Mode

Instruction contains memory address A directly.

Example: LDA 2500H => AC = Mem[2500H] or MOV AX, [2000H]
EA = A

Need large address field (16/32 bit), inflexible if code relocates.

4. Indirect Mode

Address field points to memory location that contains EA. Extra memory access.

Example: MOV AX, [BX] where BX holds pointer? Actually register indirect below; true indirect: Instruction @ 100: 500; Mem[500] = 800 => operand = Mem[800]
Often: LDA @ 1000H -> Fetch address at 1000H, then fetch operand.
EA = Mem[A]

Rare directly due to extra fetch; used for pointers where pointer address known.

5. Register Indirect Mode

Pointer in register points to memory operand.

Example:

• MOV AX, [BX] => AX = Mem[BX] (BX=1000H => load from DS:1000H)
• LDA (R1) with R1=0x2000 => operand at 0x2000
EA = (R)

Powerful for array traversal: increment R per iteration.

6. Indexed Mode

EA = R + X where X is index register or immediate offset. Two variants:

• Based / Register + Displacement: MOV AX, [BX+10H] => EA = BX + 10H
• Indexed: MOV AX, [SI+20H]

Use: Array access A[i] = Base + i. Example: Array at 2000H, element 3 (2 bytes each): MOV SI, 6 ; MOV AX, [2000H+SI]

• Auto-increment / Auto-decrement (special): After access, R = R ± size. Example: MOV AX, [SI++] (68000 (A0)+) for stack/queue.

7. Base-Indexed Mode

Combination of two registers + displacement, favored by x86.

Example: MOV AX, [BX+SI+100H] or in 32-bit: MOV EAX, [EBX+ESI*4+8]

Base = BX/BP, Index = SI/DI. EA = Base + Index + Displacement

Use: 2D array A[i][j] where Base = row base, Index = col offset or accessing struct fields where BX = struct base, SI = field index.

8. Scaled Indexed Mode (x86)

EA = Base + Index*Scale + Disp where Scale = 1,2,4,8 (size of element).

Example: MOV EAX, [EBX + ECX*4 + 0x10] (ECX = array index, each element 4 bytes, 0x10 = header offset). Common in IA-32 SIB byte.

9. Relative / PC-Relative Mode

EA = PC + Displacement.

Example: JMP Label where Label at PC + 20 ; Branch BEQ -4 ; CALL PC+8

Use: Position-independent code (PIC), branches. Displacement is signed 8/16-bit.

10. Implied / Stack Mode

Operand implicitly implied (not in field). Stack pointer assumed.

Example: PUSH AX => SP--, Mem[SP]=AX; POP AX; CLC (Clear Carry - implied flag). Zero-address instruction ADD in stack machine pops two, pushes result.

11. Input/Output Mode

Special for I/O mapped: IN AL, 40H ; OUT 40H, AL (immediate port address or via DX).

Summary Table for Exam (Draw this)

Mode	Formula	Example (8086)	Effective Address
Immediate	Op=A	MOV AX, 5	-
Register	Op=R	MOV AX, BX	-
Direct	EA=A	MOV AX, [1000H]	1000H
Reg Indirect	EA=(R)	MOV AX, [BX]	(BX)
Indexed+Disp	EA=R+Disp	MOV AX, [SI+8]	SI+8
Based Indexed	EA=Base+Index	MOV AX, [BX+SI]	BX+SI
Based Indexed +Disp	EA=Base+Idx+Disp	MOV AX, [BX+SI+100H]	BX+SI+100H
Scaled	EA=Base+Idx*S+Disp	MOV EAX,[EBX+ECX*4]	EBX+ECX*4
Relative	EA=PC+Disp	JMP +20	PC+20

Selection Criteria: Instruction frequency, address space size, supporting high-level constructs (array, struct, pointer), code density. Modern RISC uses few modes (Register, Immediate, Indexed) for simpler decode; CISC offers many for compactness.

Design and Logic of a Microprogram Sequence (7M)

1. Microprogrammed Control Unit Basics

Instead of hardwired logic, Control Unit stores microinstructions (control words) in Control Memory (CM) / microstore (ROM/Flash). Each microinstruction is a set of control signals (PCout, MARin, Read etc.). A macro-instruction (e.g., ADD) is executed as a sequence of microinstructions - called microprogram.

Wilkes (1951) proposed this concept.

Example: Fetch phase micro-sequence

T1: PCout, MARin, Read, Select4, Yin, WMFC
T2: MDRout, IRin, PC+4

2. Microinstruction Format

• Control field (CW): n bits, one per control line (horizontal) or encoded (vertical).
• Next Address field: Address of next microinstruction in CM.
• Branch/Sequencing field: Condition select + branch control.

Two types control encoding:

• Horizontal: 1 bit per signal (wide, fast, e.g., 40-60 bit microinstruction)
• Vertical: Encoded fields (narrow, slow, needs decoder)
• Nanoprogramming: Two-level.

3. Design of Microprogram Sequence Logic - Next Microaddress Generation

After executing current microinstruction at address uPC, how to find next uPC ?

Three techniques:

a) Sequential + Explicit Address:
Next address supplied in current microinstruction. Simple but wastes bits if many sequential steps.

uPC_next = Addr field of current microinstruction

b) Incremental uPC + Branch (Most common):
Use microprogram counter uPC that increments by 1 by default; if branch condition true, load address from current microinstruction.

if (Branch = 0)   uPC = uPC + 1
else if (Cond true) uPC = BranchAddress
else              uPC = uPC + 1

Uses uPC register + incrementer + MUX. Condition flags: ZERO, CARRY, OPCODE bits, INTERRUPT, BUSY.

c) Mapping via Opcode (Dispatch):
After fetch & decode, opcode bits in IR map to starting address of corresponding microprogram via mapping ROM / decoder.

Start Address = Mapping(IR[opcode])
E.g., ADD (opcode 0010) -> µaddr 0x10, SUB -> 0x18.

Implemented as: High bits from table + low bits from opcode. Often a Dispatch ROM does µAddr = Base + opcode * offset.

d) Combinations: Two-phase sequencing

Modern microprogrammed CU does:

1. Fetch sequence (fixed at µaddr 0)
2. Decode/dispatch (branch on IR opcode)
3. Execute sequence for that opcode
4. Branch back to fetch or handle indirect addressing / interrupt.

4. Logic Diagram (Next Address Generator)

         +-----+  Condition codes (FLAGS, IR bits)
         | MUX |<-----------------+
         +-----+                  |
            ^  +-------------+   +-----------+
            |  | Branch Addr |   | Condition |
            |  | from µIR    |   | Select    |
            |  +-------------+   +-----------+
+-----+ +---+----+ +--------+    +----------+   +----+
| uPC |->| CM   |->| µIR    |---->| Next Addr|-->|uPC |
| Reg |<-| (ROM)|  | (hold) |    | Logic    |   |    |
+-----+ +---+----+ +--------+    +----------+   +----+
   ^        |         | control signals ---------> to CPU datapath
   +--------+ Incrementer (uPC+1) ---------------+

Components: Control Memory (512 x 36 bit typical), Control Address Register (CAR/uPC), Control Data/Register (CDR/µIR), Next-address logic (incrementer + branch MUX + mapping PROM).

5. Example Microprogram Sequence for ADD R1, (R2)

Assume instruction: ADD R1, [R2] (R1 = R1 + Mem[R2])

µAddr : Microoperation Comment
0 : PCout, MARin, Read, WMFC Fetch opcode
1 : MDRout, IRin, PC++ Load IR
2 : R2out, MARin, Read Use R2 as address
3 : MDRout, Yin, WMFC Load operand to Y
4 : R1out, SelectY, Add, Zin ALU ADD
5 : Zout, R1in, END Write back, return to fetch

Dispatch after µaddr1: If opcode = ADD, µPC = 2, if BRA then goto branch routine, etc.

6. Design Steps (for exam)

1. List datapath control signals needed (Register in/out, ALU function, Memory Read/Write, PC inc).
2. Write micro-operation sequences for each macro instruction (fetch-decode-execute).
3. Encode signals into µinstruction control field (horizontal/vertical choice) - consider control word width vs decode delay.
4. Determine sequencing needed: sequential flow, conditional branch on flags/ opcode, subroutine calls (e.g., for interrupt handling, CALL micro-subroutine with µ-stack).
5. Choose next-address logic implementation: plain counter vs mapping ROM; assign CM addresses; generate mapping function.
6. Optimize with field encoding, nanostore, or writable control memory (WCS) for vertical microprogramming to reduce size.

Advantages: Flexible (change microprogram to change instruction set), easier debugging, supports complex CISC (IBM 360, 68000, x86). Disadvantage: Slower than hardwired due to CM access (1 cycle extra); modern RISC uses hardwired, but x86 internally translates CISC to RISC µops via microcode.

Diagram to draw: Microprogrammed CU block with CM, CAR, CDR, mapping logic, and next-address generation MUX branching back.

Effect of Instruction Set, Compiler, CPU Implementation, Cache/Memory Hierarchy on CPU Performance - CPI Analysis (7M)

Fundamental Performance Equation

$CPU_{time} = IC \times CPI \times T_{c} = IC \times CPI / f$

Where $IC$ = dynamic Instruction Count, $CPI$ = cycles per instruction (average, effective), $f$ = clock frequency, $T_c$ = clock period.

Also $MIPS = f / (CPI \times 10^6)$; $CPI_{effective} = \sum_i (CPI_i \times F_i) + Stall_{memory}+Stall_{pipeline}$ ; with memory: $CPI = CPI_{base} + MissRate \times MissPenalty$.

Every factor influences one or two of those three terms; optimal performance balances them.

1. Instruction Set Architecture (ISA) Effect

ISA defines operations, formats, addressing modes, registers.

• Program Length (IC):

  • CISC (x86): Complex instructions (REP MOVS, MUL, CALL) do more work per instruction => fewer instructions ($IC$ down) but longer and variable-length (1-15 bytes) => higher $CPI$ per instruction (5-12). Code dense, good for small memory.
  • RISC (ARM, MIPS): Simple load-store, fixed 4-byte, 3-operand => more instructions needed to do same task ($IC$ up ~30%) but each executes in 1 cycle ideal, easy pipelining.

  Example: Memory copy: x86 REP MOVSB = 1 instruction; MIPS needs loop: LW, SW, ADDI, BNE = 4 instructions. IC difference.

• Clock Rate ($f$):

  • CISC decode complex → longer critical path → lower max $f$. RISC decode trivial → higher $f$ (can pipeline deeper).

• Effective CPI:

  • ISA determines $CPI_i$ per instruction class. Variable CISC CPI varies widely; RISC keeps near 1 (plus load-use stalls). Also ISA addressing mode complexity adds extra µ-cycles.

Trade-off: $IC \downarrow$ vs $CPI \uparrow$ and $f \downarrow$.

2. Compiler Technology Effect

Compiler maps high-level code to ISA sequence; determines actual $IC$, instruction mix $F_i$, and how well CPI hides hazards.

• IC:

  • Optimization -O2 removes dead code, common subexpression elimination, loop unrolling, inlining → $IC \downarrow$ 10-50%.
  • Poor code: extra spills, redundant loads → $IC \uparrow$.

• CPI:

  • Instruction scheduling: Reorders to avoid RAW stalls, fills branch delay slots, uses forwarding effectively → stalls ↓ → $CPI_{effective} \downarrow$ from 1.5 to 1.1 (30% gain).
  • Register allocation: Keeps variables in registers → fewer loads/stores (memory CPI high) → $CPI \downarrow$ and $IC$ of memory ops ↓.
  • Choice of instructions: Uses cheap sequences (shift instead of multiply by 8) → $CPI_i$ lower.

• Clock Rate: Little direct effect, but better code may allow better branch prediction locality.

Example: Without scheduling: LW R1; ADD R2,R1 → 1 stall; scheduled: insert independent instruction between → 0 stalls → CPI saved.

3. CPU Implementation & Control Effect

Implementation is microarchitecture realizing same ISA (e.g., 486 vs Pentium for same x86 ISA).

• Clock Rate ($f$):

  • Technology: Smaller transistor, deeper pipeline (15-20 stages) enables higher $f$ (3 GHz vs 100 MHz).
  • Control: Hardwired CU → faster decode → higher $f$; microprogrammed → lower $f$ but more complex instruction support.

• CPI:

  • Pipelining: Converts $CPI$ from ~5 (non-pipelined multicycle) to ~1 + stall; $Speedup \approx n_{stages}$.
  • Superscalar / Superpipelined: Issue 2-8 instructions per cycle → $CPI <1$ (IPC >1). E.g., 4-wide processor can have $CPI_{effective}=0.25$.
  • Hazards & Stalls: Deeper pipeline increases branch mispredict penalty (15 cycles vs 3) → CPI penalty up if prediction poor.
  • Multicycle vs Single-cycle: Single-cycle CPU $CPI=1$ but long $T_c$ (slowest instr), multicycle average $CPI=3-4$ but short $T_c$ plus pipeline gives best both.

Equation with pipeline: $T_c = max(T_{stage}) + T_{latch}$. Better implementation reduces $T_{stage}$ variance.

• IC: Generally none (same ISA → same dynamic instruction count if ignoring micro-ops). But micro-op translation (x86 translates 1 CISC to 2-4 RISC µops) can affect internal IC count but not programmer visible IC.

Result: Implementation trades $CPI$ ↔ $f$. e.g., Deep pipeline: $f \uparrow 2x$ but branch miss CPI penalty rises, golden point exists.

4. Cache and Memory Hierarchy Effect

Memory hierarchy bridges CPU (ns) ↔ DRAM (100 ns) gap; determines stall component of CPI.

• Clock Rate: Cache access time is part of cycle: L1 hit ~ 1 cycle keeps $f$ high; larger cache slower but reduces miss. Design chooses split.

• Effective CPI - Dominant:

  • No cache: Every $LW/SW$ suffers 50-100 cycles miss → $CPI_{effective} = CPI_{base} + Memory\_access\_per\_instr \times (1 - h) \times MissPenalty$.
  • With hierarchy: $T_{eff} = h_1 T_{L1} + (1-h_1)[h_2 T_{L2} + (1-h_2)T_{RAM}]$.
  • Example: Base CPI=1.0, 30% loads/stores, miss rate 5%, penalty 20 cycles → $CPI =1.0 +0.3*0.05*20 =1.30$ (+30% time). Improving hit rate from 95% to 98% via larger cache → CPI → 1.12.

• Program Length (IC):

  • Larger block/cache with prefetch can reduce instruction fetch IC stalls but adds overhead of coherence/ TLB misses. Prefetch / O-O-O hides.

• Interactions:

  • Larger cache → lower miss rate → $CPI\downarrow$ but larger access time → may limit $f$ and higher power/cost.
  • Write policy: Write-back reduces bus traffic → less stall.

Overall $CPU_{time}$ with hierarchy: $CPU_{time} = IC \times (CPI_{execution} + Stall_{mem}) \times T_c$.

Summary Matrix (Mark-Scoring Table)

Factor	Primary effect on	Direction	Example justification
ISA - CISC complexity	$IC \downarrow$	fewer instr	REP MOVS vs loop
	$CPI \uparrow$, $f\downarrow$	each CISC takes micro-steps, complex decode	CPI 5 vs 1
Compiler optimization	$IC \downarrow$	eliminate	DCE -20%
	$CPI \downarrow$	schedule to avoid stalls	reorder LW-USE
CPU Implementation (pipeline, superscalar, hardwired)	$f \uparrow$	deeper pipe, faster tech	3 GHz vs 33 MHz
	$CPI \downarrow$ (~1 to <1)	overlap, parallel issue	4-wide IPC=3
Cache Hierarchy	$CPI_{eff} \downarrow$ greatly	hit reduces stall	$h$=95% saves 20 cycles
	$f$ slightly ↓ if large	size ↔ speed	L1 32KB 2 cycles vs L2 1MB 10 cycles

Combined Formula Justification:
$Performance \propto 1 / CPU_{time} \propto f / (IC \times CPI_{base+stall})$

To improve performance: Reduce IC via RISC? Actually need product minimal. Recent trends: Keep ISA fixed (x86), aggressively improve Compiler, Implementation (O-O-O, branch prediction, speculative), and Hierarchy (multi-level cache, prefetch, TLB) to hide $CPI_{stall}$ while pushing $f$ via scaling. Amdahl emphasizes bottleneck - e.g., even infinite $f$ but 20% memory stalls caps speedup.

For 7M answer: Write equation first, then 4 subsections each stating effect on IC, f, CPI with 2-line justification + numeric example, conclude with trade-offs matrix.

Addressing Modes

Definition: The technique used to specify the operand address in an instruction is called addressing mode. It tells how Effective Address (EA) of operand is calculated.

5 Important Addressing Modes with Examples (assume 8-bit opcode + address field)

1. Implied / Implicit Mode

   • Operand is implicit in opcode itself.
   • CLC (clear carry), STC, HALT
   • EA not needed. Size 1 byte, fast.

2. Immediate Mode

   • Operand itself is in instruction.
   • MOV A, #30H ; ADD #5 → AC ← AC + 5
   • EA = PC+1 (operand field). Fast, no memory reference but limited range ($0$ to $2^{24}-1$ for 24-bit field).

3. Direct / Absolute Mode

   • Address field gives effective address directly.
   • LOAD A, [1000H] → AC ← M[1000H]
   • EA = Address field. Simple but needs $24$ bits to address $16$ MB only, one memory access.

4. Indirect Mode

   • Address field contains address of address.
   • LOAD A, @2000H → AC ← M[M[2000H]]
   • EA = M[Address field]. Can address $2^{32}$ via pointer but needs 2 memory accesses, slow.

5. Register Mode

   • Operand in register.
   • ADD R1, R2 → R1 ← R1+R2 ; MOV A,B
   • EA = Register ID. Very fast, no memory, limited registers.

6. Register Indirect Mode

   • Register holds address of operand.
   • LOAD A, (R1) where R1=2000H → AC ← M[R1]
   • EA = (R). Flexible for pointer/array traversal.

7. Indexed / Base-Relative Mode (extra)

   • LOAD A, 1000H(X) → EA = X + 1000 where X is index register. Useful for arrays. EA = R + displacement.

Comparison Table (5+ modes)

Feature	Immediate	Direct	Indirect	Register	Register Indirect	Indexed
EA =	operand	A	M[A]	R	M[R]	R + disp
Memory refs	0	1	2	0	1	1
Speed	Fastest	Medium	Slow	Fastest	Medium	Medium
Address range	Limited to field	$2^{24}=16$MB	Full $2^{32}$	$2^{k}$ regs	Full	Full
Use	Constants	Global var	Pointers	CPU ops	Pointers/tables	Arrays
Instruction size	1 word	1 word	1 word	1 word	1 word	1 word+disp
Example	ADD #5	LD 1000H	LD @1000H	ADD R1,R2	LD (R1)	LD 1000(X)

Effective Address Calculation summary:

• Direct: $EA = A$
• Immediate: $Operand = A$
• Indirect: $EA = M[A]$
• Register: $EA = R$
• Indexed: $EA = R + A$

Direct needs large field for address; indirect saves field but extra fetch; register fastest; indexed best for relocatable/array structures.