COMPUTER ORGANIZATION & ARCHITECTURE

A pipeline stage

(i) Is sequential circuit
(ii) Is combination circuit
(iii) Consists of both sequential and combinational circuit
(iv) None of these

The performance of a pipelined processor suffers if
(i) The pipeline stages have different delays
(ii) Consecutive instruction are dependent on each other
(iii) The pipeline stages share hardware resources
(iv) All of these

Which of the following has no practical usage?

(i) SISD
(ii) SIMD
(iii) MISD
(iv) MIMD

What does a branch prediction mechanism in a CPU help reduce?
a) Data hazards
b) Control hazards
c) Structural hazards
d) Clock cycle delays

Which technique is used to handle data hazards in pipelining?
a) Increasing memory size
b) Instruction scheduling
c) Parallel processing
d) Increasing clock speed

(i) The situation wherein the data of operands are not available is called

(i) data hazard
(ii) stock
(iii) deadlock
(iv) structural hazard

The stalling of the processor due to the unavailability of the instruction is called as:
(i) Control hazard
(ii) Structural hazard
(iii) Input hazard
(iv) None of the above

In case of pipelining processor, loop buffer is

• (i) very high speed memory maintained by the instruction fetch stage
• (ii) very high speed memory maintained by the instruction decode stage
• (iii) very high speed memory maintained by the instruction execute stage
• (iv) None of the above

Briefly explain the conflicts in instruction pipeline.

What do you mean by data hazards in pipelining?

Pipeline speedup ideally increases with:
(i) Number of control units
(ii) Size of RAM
(iii) Number of pipeline stages
(iv) Size of cache

What do you mean by array processors? How are they different from scalar processors?

What are the hazards in pipeline architecture? Explain its types with suitable example.

Explain Flynn’s classification of computer system architecture.

Discuss Flynn’s classification of computer.

3. A program runs on a 10 GHz CPU with the instruction mix and corresponding clock cycle count as given in the table:

Instruction type	Clock cycle count	Instruction count
Control transfer	5	5000
Data transfer	4	4000
Floating point	2	2000
Integer	1	1000

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Determine the following:

• (a) CPI
• (b) Execution time
• (c) MIPS rate for program

Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

What are the different conflicts that will arise in pipeline (elaborate)? How do you remove the conflicts?

What is meant by pipelining? Why do we require instruction pipelining? Explain its working procedure. Discuss the pipeline performance measures.

A non-pipeline system takes 50 seconds to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10 seconds. Determine the speedup ratio of the pipeline for 100 tasks.

What are pipeline hazards? Explain different types of hazards in pipelining.

A non-pipelined processor has a clock rate of $2.5$ GHz and an average CPI (cycles per instruction) of $4$. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to $2$ GHz.

(a) What is the speedup achieved for a typical program?

(b) What is the MIPS rate for each processor?

Explain the basic concepts of pipelining, including speedup and throughput. Discuss pipeline hazards.

Describe parallel processors and the problem of cache coherency in shared memory systems.

The stage delays in a four-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. What would be the throughput increase (in percentage) of the pipeline?

What are hazards in pipeline architecture? Explain its types with suitable examples.

What is an array processor? Explain SIMD array processor with a suitable example.