COMPUTER ORGANIZATION & ARCHITECTURE

A direct mapped cache memory with $n$ blocks is nothing but which of the following set
associative cache memory originations

(i) 0-way set associative
(ii) 1-way set associative
(iii) 2-way set associative
(iv) n-way set associative

A computer with cache access time of $100\,ns$, a main memory access time of $1000\,ns$, and a hit ratio of $0.9$ produces an average access time of

(i) $250\,ns$
(ii) $200\,ns$
(iii) $190\,ns$
(iv) None of these

(e) For converting a virtual address into the physical address, the programs are divided into
(i) pages
(ii) frames
(iii) segments
(iv) blocks

Which cache replacement algorithm removes the least recently used block.
(i) FIFO
(ii) LRU
(iii) Random Replacement

How many 128x8 bit RAMs are required to design 32 kx 32 bit RAM?
(i) 512
(ii) 128
(iii) 1024
(iv) 32

(j) The DMA controller has ____ registers.

(i) 4
(ii) 2
(iii) 3
(iv) 1

A computer with 32-bit wide data bus uses 1K, X, and 8 static RAM memory chips.
What is the smallest memory that this computer has?
a) 12K
b) 10K
c) 8K
d) 16K
e) 24K

(b) How is virtual memory managed using paging and TLB? Explain with suitable example.

What do you mean by locality of reference?

What do you mean by cache coherence problem?

The average memory access time for a machine with a cache hit rate of 90% where the cache access time is 10 ns and the memory access time is 100 ns is

• (i) 55 ns
• (ii) 45 ns
• (iii) 90 ns
• (iv) 19 ns

How many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes?

Why is the wait-for-memory-function-completed step needed when reading from or writing to the main memory?

The minimum time delay between the initiations of two independent memory operations is called

• (i) access time
• (ii) cycle time
• (iii) transfer rate
• (iv) latency time

What is the importance of cache memory in a computer?

Define locality of reference.

Give the features of a ROM cell.

Define hit ratio and explain its significance.

In cache memory, FIFO and LRU are examples of:
(i) Mapping techniques
(ii) Addressing techniques
(iii) Replacement algorithms
(iv) Write policies

(3). Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields—the first byte contains the opcode and the remainder the immediate operand or an operand address.

(a) What is the maximum directly addressable memory capacity (in bytes)?

(b) Discuss the impact on the system speed if the microprocessor bus has—
    i) a 32-bit local address bus and a 16-bit local data bus, or
    ii) a 16-bit local address bus and a 16-bit local data bus.
(c) How many bits are needed for the program counter and the instruction register?

Explain the concept of virtual memory with the help of a diagram. Explain how virtual address is mapped to actual physical address.

Explain in detail the hierarchical memory structure with a neat and labelled diagram.

A 4-way set associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. Find the number of bits for TAG, SET, and WORD fields in the address generated by CPU.

How is the virtual address mapped into physical address? What are the different methods of writing into cache?

What is associative memory? Explain with the help of a block diagram. Also mention the situation in which associative memory can be effectively utilized.

What is swapping and how is it useful in memory management?

A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor’s addresses are interpreted.

Explain different cache replacement algorithms used in memory management.

Discuss the different mapping techniques used in cache memories and their relative merits and demerits.

Give an integrated diagram showing the TLB and cache operations for a logical/virtual address generated by a processor.

Differentiate between hardwired programmed control and microprogrammed control.

Discuss the different ways in which ROM can be programmed.

Illustrate what are the challenges associated with concurrent access to memory in parallel processing?

Consider a direct mapped cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, 8, 0, 63, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24. What would be the status of cache blocks (block numbers residing in cache) at the end of the sequence.

Define paging in memory management and write its advantages.

Differentiate between expansion and extension of memory.

Describe organization of a typical RAM chip. Differentiate between static RAM chip and dynamic RAM chip.

What is a page fault? What does a page fault signify? Explain the different page replacement algorithms which determine the page to be removed in case of full memory.

A virtual memory system has an address space of 8k words, memory space of 4k words and page & block size of 1k words. The following page reference changes occur during a given time interval:

4, 2, 0, 1, 2, 6, 1, 4, 0, 1, 0, 2, 3, 5, 7
Determine the four pages that are resident in main memory after each page reference change if the replacement algorithm used is

• (i) FIFO
• (ii) LRU.

Explain swapping. Why is it used in memory management?

Explain virtual memory. Explain the role of logical as well as physical address.

Explain in detail the three mapping procedures related to cache memory.

Explain cache memory organization. Discuss mapping techniques (direct, associative, set-associative), replacement algorithms, and write policies.

How many ROM chips are required to produce a memory capacity of 4096 bytes? How many address lines are required to access the 4096 bytes? How many of these addresses will be common to all these chips?

Write short notes on: Paging

Write short notes on: Memory interleaving

Write short notes on: Locality of reference

Discuss memory hierarchy design principles. Explain how access time, cost, and size influence memory organization.